Example image of eyePlorer eyePlorer map for 'Netlist': Electronic design automation Hardware description language Simulation Verilog VHDL Capacitor Integrated circuit Resistor SPICE EDIF Circuit extraction Horizontal constraint graph Vertical constraint graph CAD Navigation Silicon compiler JHDL NAND logic NOR logic Semiconductor intellectual property core Schematic editor Signoff (electronic design automation) Carl Ebeling Standard cell Capture CIS Formal equivalence checking Layout Versus Schematic Place and route Placement (EDA) Intel 8051 OASIS (Open Artwork System Interchange Standard) Design For Test GEDA NET Application-specific integrated circuit List of file formats Signal integrity Field-programmable gate array Zilog Z80